1. Field of the Invention
The present invention relates to a log compressing circuit, such as an operating circuit for measuring a distance, which is arranged to perform log compression about an input signal, and more particularly to a log compressing circuit which serves to clamp an output voltage when performing log compression at a predetermined voltage.
2. Description of the Background Art
The inventors of the present application acknowledge that such a log compressing circuit as applied to a distance measuring circuit for an auto-focus camera has been arranged to clamp the output voltage if it exceeds a predetermined clamp voltage. The electric connecting arrangement of the known log compressing circuit will be described as referring to FIG. 1.
As shown, an input current I80 is guided to a base of a transistor Q91, so that the current I81 amplified by the transistor Q91 may flow through a compressing diode Q92. Hence, the voltage Vbe92 between the terminals of the compressing diode Q92 may be represented as follows, because the compressing diode Q92 is composed of a transistor having its base and collector connected to each other. EQU Vbe92=kT/q* ln (I81/Io92) (91st expression)
where Io92 denotes a reverse saturation current between the base and the emitter of the compressing diode Q92. As is obvious from the expression, the current I81 is log-compressed as the voltage Vbe92.
The impedance conversion is performed about this voltage Vbe92 in a transistor Q93 which is an emitter follower. Then, at an output OUT9, the following voltage appears. EQU Out9=Vcc-(Vbe92+Vbe93) (92nd expression)
where Vcc is a reference voltage value and Vbe93 denotes a voltage applied between the base and the emitter of the transistor Q93.
On the other hand, transistors Q94 to Q99 and Q90 and constant current I95 to I97 form a clamp circuit. The voltage at the base of the transistor Q96 is fixed at a constant voltage through the effect of a diode Q90 and a transistor Q99 for impedance conversion. As such, the reduction of the input current I80 lowers a voltage between the terminals of the compressing diode Q92. If the base voltage of the transistor Q95 goes beyond the base voltage of the transistor Q96, a collector current I83 of the transistor Q96 is larger than a collector current I82 of the transistor Q95. This results in making the current of I85=I83-I82 flow through the base of the transistor Q94. Hence, the base current of the transistor Q95 and the emitter current of the transistor Q93 are pulled by the emitter current of the transistor Q94, so that the base voltage of the transistor Q95 may be made lower. This feedback operation keeps the base voltage of the transistor Q95 equally balanced with the base voltage of the transistor Q96, thereby clamping the voltage Out9 by the base voltage of the transistor Q96.
The clamp voltage is defined by the currents I86 and I87 flowing through a diode Q90, a transistor Q99 and constant current sources I96 and I97. Assuming that the voltage between the terminals of the diode Q90 is denoted by Vbe90 (the diode Q90 is composed of a transistor having its base and collector connected to each other), Vbe90 can be represented by: EQU Vbe90=kT/q* ln (I87/Io90) (93rd expression)
wherein Io90 denotes a reverse saturation current between the base and the emitter of the diode Q90. As such, the base voltage V96 of the transistor Q96 can be represented by: EQU V96=Vcc-(Vbe90+Vbe99) (94th expression)
where Vbe99 denotes a voltage between the base and the emitter of the transistor Q99 operated as an emitter follower.
On the other hand, assuming that Ix81 denotes a value of the current I81 given when clamping is ready to start, when the current I81 becomes I81=Ix81, the following equation is established. EQU Vce93=Vce99
where Vce93 denotes a voltage between a collector and an emitter of the transistor Q93 and Vce99 denotes a voltage between a collector and an emitter of the transistor Q99.
By representing the equation by using the 91st to the 94th expressions, the following equations can be established. EQU Vbe92+Vbe93=Vbe90+Vbe99 EQU kT/q* ln (Ix81/Io92)+Vbe93=kT/q* ln (I87/IO90)+Vbe99
Now, assume that each combination of the diodes Q92 and Q90, the transistors Q93 and Q99 and the constant current sources I93 and I96 is arranged of the similarly patterned elements. On the assumption, Io92=Io90 and Vbe93=Vbe99 are established. Hence, Ix81=I87 is established as well.
As such, the clamp level at the current I81 flowing through the diode Q92 is denoted by I87 and the clamp level Ix81 is set as a current value of the constant current value I97.
The clamp level Ix81 in the known arrangement does not depend on the variety of the transistor h.sub.FE resulting from the processing difference of each wafer. However, as viewed from the input current I80 side, the current Ix80 can be represented by: EQU Ix80=Ix81/h.sub.FE 91
where Ix80 denotes a value of the input current flowing when clamping is ready to start and h.sub.FE 91 denotes an amplification factor of the transistor Q91. That is, the difference of the amplification factor of the transistor Q91 resulting from the difference of the process appears as the difference of a clamp level as viewed from the input side. This has been a disadvantage of the known log compressing circuit.